package device
import chisel3._
import chisel3.util._
import bus._
import top.Settings

class device extends Module{
  val io = IO(new Bundle() {
    val in = Flipped(new AXI4())
  })

   val addrSpace = List(
     (0x80000000L, 0x80000000L),
     (Settings.getLong("MMIOBase"), Settings.getLong("MMIOSize")), // external devices
   )
  val RAM = Module(new AXI4RAM(memByte = 128 * 1024 * 1024))
  //val mmio = Module(new MMIO)
  val uart = Module(new AXI4UART)
  val xbar = Module(new AXI4Crossbar1toN(addrSpace))
  def isMMIO(addr: UInt): Bool = {
    addr < "h80000000".U
  }

  io.in <> xbar.io.in
  RAM.io.in <> xbar.io.out(0)
  uart.io.in <> xbar.io.out(1)

}
